multi-channel (more than one CCD and readout port)
low-noise
relatively fast (16-bit ADC's)
extensively used at the world's best telescopes:
Gemini, Keck, ESO (for their autoguiders and WFS), SALT, WHT, AAT, UKIRT,
Subaru (for FMOS), Grantecan (for EMIR).......
existing expertise at UKATC with this technology
aim of our contribution to WP5:
design and manufacture high-voltage (50V swing) clock driver board
for the SDSU, enabling it to drive EMCCD's. This will allow experience to be
gained quickly in running EMCCD's, and offer a significant deliverable
which will be of interest to other users of SDSU controllers
status of our contribution to WP5:
first version of high-voltage clock board designed, manufactured and
tested (Q4 2004)
future plans for our contribution to WP5:
test new board with EMCCD's procured as part of WP2 (Q2-Q3 2005)
design, manufacture and test second (and final) version of high-voltage
clock board (Q3-Q4 2005)
(speed up SDSU by using new drop-in 5MHz (14-bit) ADC's in video
boards, and double speed of timing board to 25 MHz using 2 fibre links
and 2 PCI cards)
spend, to date, on our contribution to WP5:
SDSU controller: 12 kpounds
data acquisition PC: 2 kpounds
high-voltage clock board: 2 kpounds
staff effort (at UKATC): 4 months
future spend on our contribution to WP5:
final version of high-voltage clock board: 2 kpounds
